Clocking of logic circuits



March 2, 1965 J. R. WILKINSON 3,171,972

CLOCKING 0F LOGIC CIRCUITS Filed May 12. 1960 "5 CLOCK k f OLD U U 1.!cum I I P I 'looK" P2 1 LOGIC 0 aur ur l P 4 #2 P 7! "LT Ll Li l OUTPUTI? czoclf 2 LOGIC a INVERTER OUTPl/T H #2 our/ ur n/vp INVENTOR Jaw/v7?. MA #01490 P6 RF. IIYPl/T ATTORNEYS United States Patent C) 3,171,972CLOCKING F LOGIC CIRCUITS John R. Wilkinson, Allendale, N.J., assignorto Sperry Rand Corporation, New York, N.Y., a corporation of DelawareFiled May 12, 1960, Ser. No. 28,796 7 Claims. (Cl. 30788.5)

This invention relates to clocking of logic circuits and moreparticularly to clocking of a regenerative bistable logic circuit.

Logic circuits operating on a binary number system, employ elementswhich are capable of being switched from one state to another.Transistors are readily employed as such elements since application ofproper potentials to a transistor will cause it to turn on or turn oif,thereby switching its state. Two transistors can be arranged in tandemwith a feedback path to form a regenerative bistable circuit capable ofbeing switched in state on a proper combination and application ofbinary signals. This invention employs a regenerative bistable logiccircuit, such as the transistor type just referred to though nolimitation thereto is intended, together with circuit means forcontrolling the resultant state of the circuit in accordance with thebinary senses of both a binary input signal and a binary control orclock pulse signal.

It is therefore an object of this invention to provide a bistablelogical circuit, which includes a feedback path under the control of abinary control signal, with means for causing the final state of thecircuit to be dependent on the sense of the binary input signal onlywhen the binary control signal is in a predetermined one but not theother of its senses regardless of the initial state of the logicalcircuit.

Another object of the invention is to provide a transistorizedregenerative circuit as in the foregoing object, whose :state can beswitched only when the clock pulse is in that predetermined one of itssenses.

Still other objects of this invention will become apparent to those ofordinary skill in the art by reference to the following detaileddescription of the exemplary embodiments of the apparatus and theappended claims. The various features of the exemplary embodimentsaccording to the invention may be best understood with reference to theaccompanying drawings, wherein:

FIGURE 1 is a schematic diagram of a regenerative bistable logiccircuit,

FIGURE 2 is a block diagram of the circuit of FIG- URE 1,

FIGURE 3 shows idealized signal waveforms for various points in FIGURE2,

FIGURE 4 is a block diagram of an improved regenerative bistable logiccircuit and its associated logic control elements, and

FIGURE 5 illustrates signal waveforms related to the circuitry of FIGURE4.

In FIGURE 1 a bistable circuit is formed by transistors T T and afeedback path which runs from collector of transistor T through diodes DD and resistor R back to the base 12 of transistor T The voltage dividercomprising resistors R R and R connected between positive and negativevoltage sources provides bias for the base 12 of transistor T Thevoltage divider R R and R is identical to the divider R R R and isconnected between positive and negative voltage sources to providesimilar bias for collector 14 of transistor T and base 16 of transistorT Bias for collecter 10 of transistor T is provided via resistor R,which is connected to a negative voltage source. The emitters 18 and 20of transistors T and T are both 3,171,972 Patented Mar. 2, 1965 "icecoupled to ground. Junction A between diodes D and D is biased byresistor R connected to a positive voltage source. Transistors T and Tare additionally provided with input coupling capacitors C and Cconnected to the junction between R R and R R respectively.

A binary or logic input signal applied through diode D is A.C. coupledto transistor base 12 by condenser C and DC. coupled thereto viajunction B and resistor R Similarly, the output from collector 14 isA.C. coupled to base 16 by condenser C and DC. coupled thereto throughresistor R A binary control signal in the form of a clock pulse may beapplied to the circuit through diode D to junction A. A mid-output maybe taken from the collector 14 of transistor T as at terminal No. 1,while the normal or end output can be taken from the collector 10 oftransistor T via output terminal No. 2.

The section of the circuit comprising transistors T T and their relatedbias and coupling means form a pulseformer which is made bistable innature by the feedback path from its output to its input, the feedbackpath being under the control of the clock signal. The state of thebistable circuit of FIGURE 2 may be denoted by the binary numbers 0 and1 in an arbitrarily selected manner. In the following discussion, a 0refers to a pulse or voltage condition more negative than a 1 pulse orvoltage condition. The bistable circuit may therefore be said to be in a1 state when the normal output No. 2 is relatively positive (in thisinstance ground), and in a 0 state when that output is negative. Themid-output No. 1 is the complement of output No. 2.

In the following exemplary discussion, the resistors R and R have avalue of 27,000 ohms, the resistors R R have a value of 1,500 ohms, theresistors R R R R have a value of 8,200 ohms, the coupling capacitors CC have a value of micromicrofarads, and the voltage sources are plus 12volts and minus 15 volts.

In FIGURE 1, a negative input or binary 0 to the base 12 of transistor Tcauses it to conduct, placing its collector at ground and producing a 1output. This results in base 16 going positive, turning off transistor Tand placing output No. 2 at a negative potential to effect a 0 state forthe bistate circuit as a whole. The voltage divider consisting of theresistor R R and diode D between the plus 12 and minus 15 volt sourcesplaces junction A at approximately minus 3 volts. If the control signalor clock is relatively positive effecting a binary 1 during what may betermed a clock hold period, diode D is cut off, junction B remainsnegative assuming the logic input through diode D is 0, and transistor Tkeeps conducting to maintain the 0 condition. When the clock voltagegoes negative then to represent a binary 0 during which time the clockmay be said to be in a look period, the 0 condition is still maintained.

On the other hand a relatively positive input or binary l to the base 12cuts off transistor T and turns on transistor T placing output No. 2 ata 1 condition. This, if the clock voltage is relatively positive, putsjunction A at ground through the feedback path from the collector '10 tothe voltage divider, so junction B is at ground through diode D andoutput No. 2 stays in the 1 condition while the clock is positive duringthe hold period. When the clock looks, however, junction A goesnegative, diode D clamps junction B at the clock negative voltageassuming the logic input through diode D is then 0, turning ontransistor T and thereby making output No. 2 go negative, i.e. to a 0condition.

Therefore, unless the logic input is 1, the clock always changes the No.2 output to a 0 condition by deactivating the feedback loop during thelook time. The complete operation of FIGURE 1 will be described withreference to the block diagram of FIGURE 2 and the 3 voltage waveformsshown in FIGURE 3. The elements D D and R of FIGURE 1 form .an Andcircuit, while elements D D and R3 form an Or circuit. FIGURE 2represents the circuit of FIGURE 1 using a block diagram form for theAnd circuit 22, Or circuit 24, and pulseformer circuit 26 for easeof'discussion as to the circuit operation. The pulseformer has someslight inherent delay in changing its output condition upon receipt ofchange in. its input signal, and this delay is shown in the P waveformof FIGURE 3.

From FIGURES 2 and 3, it will be seen that if the pulseformer output Pinitially is a 1 during the .hold time or 1 condition of the clockcontrol signal P then the And input P to the Or circuit will be 1,therefore, regardless of the sense of the logic input'signal P duringthat hold time the input P to the pulseformer from the Or circuit willbe 1 and the pulseformer will be maintained in the 1 state at leastuntil the next clock lock time. At that time, the control signal P is sothe And input P to the Or circuit is 0. Consequently,the input P to thepul'seformer .at that time depends upon the sense of the logic signal Pto the Or circuit. That is, the pulseformer input P will then be 0 whenthe logic input is O, or will be 1 when the logic input is 1. Therefore,the resultant state of the pulseformer follows or is noncomplementary tothe logic input during the clock look time.

When output P is initially 0 during the hold time.

of the clock P the And input P to the Or circuit will be 0, and again,the pulseformer input P will depend upon the sense of the logic input Pto the Or circuit. Similarly, when the initial output P is 0 and theclock P looks the And input P to the Or circuit will remain 0 and thepulseformer input P will still depend upon the sense of the logic inputP to the Or circuit, The results of the circuit analysis for the abovecombinations of conditions are summarized in Table I The above summarycorresponds to the waveforms shown in FIGURE 3 and indicates the result'of the final output in accordance with the senses of the binary logicand control signals. As shown inthe summary, the circuit of FIGURE 2invariablymaintains the puls'eformer output P in its initial 1 conditionduring the clock ,hold (1) time regardless of the sense of the logicinput, and causes the resultant P -output during the following look time(0) to be non-complementary to the logic input P When output P isinitially'O, a similar situation exists during the look time in that theP resultant output depends on the reuse of the P logic signal. Asdistinguished from when the P output is initially 1, however, an initialP output of 0 is not invariably maintained during the hold timeregardless of the sense of 'the logic signal since as the above tableshows the resultant output then is dependent on whether the logic signalis a 001 1.

This last situation is not desirable as the bistable circuit will beswitched from .0 to 1 .state for a logic input of 1 during the clockhold time. It is preferable to maintain the bistable circuit in itsstate during the clock 'hold time and only allow it to be set to 1 orcleared :to 0 duning the clock look time. This can be accomplished by acircuit as represented inthe block diagram of FIGURE 4, which is thesame as that shown in FIGURE 2 with the addition of a second Or circuit28 followed by inverter 30. In FIGURE 4, the logic signal P is stateduring this clock hold time.

the inverter will be 0 if either of the inputs P and P coupled as aninput to the added Or circuit 28 with the output of the inverterreplacing the P signal input to Or circuit 24. The new Or circuit 28also receives the P 'clock signal. vThe inverter may be like either ofthe transistor stages of the pulseformer of FIGURE 1 without a feedbackpath. As will become fully apparent in thefollowing description of theoperation of FIGURE 4 during which reference is made to the voltageWaveforms shown in FIGURE 5, the Or and inverter circuits 28, 30together operate as a true Or-Inverter or Or-Not logical circuit.

Assume the pulseformer output P to be 1 during the clock hold time.Therefore, the output P from And circuit 22 will be 1, the output P fromOr circuit 24 will be 1 and the pulseformer will be maintained in the lThe output P from to Or circuit 23 are 1. P will only be 1 if both ofthe inputs P andP are 0; When the clock looks, the And outputl will goto Oytherefore the Or output P will depend on the inverter output P Whenthe logic input P is 1, the inverter output will be 0, and since both ofthe inputs to Or circuit 24 are then 0, P Will be 0, setting thepulseformer to 0. When the logic input P is 0, the inverter output willbe 1, the output P will then be 1, and the pulseformer will bemaintained at 1. However, it will be noted that due to the inherentdelay in the inverter and in the pulseformer, the And output P will goto 0 slightly before the inverter output P reaches 1. The pulseformerwill therefore clear to 0 during the look time. The period for which itstays at 0 will be equal to the time .of the-delay in the inverter,since as soon as the inverter, output P reaches 1, the pulseforrner willbe set back to 1. This flip to 0 by the pulseformer has such a shorttime duration that its effect in the output R, can be eliminated byordinary circuit means and presents no problem or limitation on the useof the circuitry of FIGURE 4. It can be stated, therefore, that thepulseformer is effectively set to 1 during the clock look 'ing the clockhold time, the And output P will be 0,

and since the inverter output P is also 0 regardless of the sense .ofthe logic input, the Or output P will be 0, maintaining the pulseforrnerin its 0 state. When the clock looks, the And output P remains 0, butthe inverter output P depends upon the logic input P When P is :0, theinverter output is 1, therefore P is 1, setting the pulseformer to the 1state. When P is 1, the inverter output is 0, and the Or output P is O,maintaining the initial 0 state. The results of the circuit analysis forthe preceding combinations of conditions are summarized in the followingtable:

Table 11 Initial Output P4 Clock Pr Logic P Resultant Output P 1 1 or 01 l 0 1 0 0 0 1 1 1 or 0 0 o 0 1 0 '0 0 1 The above summary correspondsto the waveforms shown in FIGURE 5, overlooking the momentary flip ofthe pulseformer, and shows the results of the final output in accordancewith the senses of the binary logic and control signals. As indicated by,the summary, the circuit of FIGURE 4 maintains its initial output stateduring the clock hold time, regardless of the sense of the logic input,and changes its state only during the clock look time and then only whenthe sense of the logic input is non-complementary to the sense of theinitial output. The resultant P outputduring the look times isconsequently the complement of the P logic signal, but if thenon-complernent thereof is desired that can be obtained from the No. 1or mid-output terminal of the pulseformer.

A bistable logical circuit has been provided, therefore, in which thefinal state of the circuit is dependent on the sense of the binary inputsignal only when the binary control signal is in a predetermined one(look) but not the other (hold) of its senses, regardless of the initialstate of the logical circuit.

This invention can be used with either single phase or multi-phaseclocking systems. In multi'phase systems, the look portions ofsuccessive phases must not overlap. In single phase systems, there mustbe a suflicient delay between successive clocked stages so that theinput to a clocked stage does not change during the look time due to achange in the input of the previous clocked stage. This invention usesfewer components than were previously required and causes less circuitdelay, allowing higher operational speeds. Also, only one polarity ofclock pulse is necessary. The output of the clocked Or-inverter can beused as the input to a number of bistable circuits if desired.

Thus, it is apparent that this invention successfully achieves thevarious objects and advantages herein set forth.

Modifications of this invention not described herein will becomeapparent to those of ordinary skill in the art after reading thisdisclosure. Therefore, it is intended that the matter contained in theforegoing description and the accompanying drawings be interpreted asillustrative and not limitative, the scope of the invention beingdefined in the appended claims.

What is claimed is:

1. In an arrangement for indicating the sense of a binary input signaland including a bistable circuit whose output is returned to an input ofsaid circuit in accordance with the sense of a binary control signal,the improvement comprising means including means coupled to said inputand performing an Or-Not function, coupled to receive both of saidbinary signals for controlling the final state of said circuit inaccordance with the instant binary sense of the input signal regardlessof the initial state of said circuit but only when said control signalis in a predetermined one of its senses.

2. An arrangement as in claim 1 wherein the Not function is performed bya binary signal inverter coupled at its output to the said input of saidbistable circuit.

3. Apparatus for indicating the sense of a binary input signalcomprising a bistable circuit having a feedback path for coupling anoutput of said circuit to an input thereof means in said path forcontrolling the feedback in accordance with a binary control signal, andfurther means including an Or-Not circuit coupled to receive said inputand control signals and applying its output to the said input of saidbistable circuit for controlling the final state of said circuit inaccordance with the instant binary sense of said output signalregardless of the initial state of said circuit but only when saidcontrol signal is in a predetermined one of its senses.

4. Apparatus as in claim 3 wherein said further means includes means toOr the said input and control signals and means coupled to said inputfor changing the binary sense of the Or means output.

5. Apparatus as in claim 4 wherein the sense changing means is aninverter.

6. Apparatus for indicating the sense of a binary input signalcomprising an Or-inverter circuit coupled to receive the said binarysignal, an Or circuit coupled to the Or-Inverter circuit output, abistable circuit coupled at an input to the output of said Or circuit,the output of the bistable circuit furthest from its said input beingreturned to that input through a feedback path including first an Andgate and then said Or circuit, and a binary control signal coupled as aninput to both the And gate and the Or-Inverter circuit, whereby thebistable circuit can only change its state according to a logicalcombination of said binary input and control signals when the controlsignal is in a predetermined one of its senses and will maintain itsstate when the control signal is in its other sense regardless of thesense of the input signal.

7. Apparatus for controlling the switching of a bistable circuit inaccordance with the binary sense of a control signal comprising: firstand second switching elements having an output electrode and a controlelectrode means connecting the output electrode of said first switchingelement to the control electrode of said second switching element; andmeans including gating means responsive to a control signal connectingthe output electrode of said second switching element to the controlelectrode of said first switching element, such that the binary state ofsaid bistable circuit can be switched only when said control signal isof a predetermined binary sense.

References Cited in the file of this patent UNITED STATES PATENTS2,827,566 Lubkin Mar. 18, 1958 2,898,479 McElroy Aug. 4, 1959 2,909,678Jensen Oct. 20, 1959 2,918,586 Curtis Dec. 22, 1959 OTHER REFERENCESPulse and Digital Circuits, Millman and Taub, TK 7835 M55, pages409-411.

1. IN AN ARRANGEMENT FOR INDICATING THE SENSE OF A BINARY INPUT SIGNALAND INCLUDING A BISTABLE CIRCUIT WHOSE OUTPUT IS RETURNED TO AN INPUT OFSAID CIRCUIT IN ACCORDANCE WITH THE SENSE OF A BINARY CONTROL SIGNAL,THE IMPROVEMENT COMPRISING MEANS INCLUDING MEANS COUPLED TO SAID INPUTAND PERFORMING AN OR-NOT FUNCTION, COUPLED TO RECEIVE